I. Field of the Invention
The present invention relates to partially depleted silicon-on-insulator technology, and more particularly to techniques for estimating the body voltage of digital integrated circuits and partially depleted silicon-on-insulator (“PD-SOI”) technology.
II. Description of the Related Art
Silicon-on-insulator (“SOI”) technology has long been used for radiation-hardened or high-voltage integrated circuits. In more recent years, SOI has also been considered for us as a technology for high-performance, low-power deep-submicron digital integrated circuits. For digital applications, fully-depleted devices have been largely abandoned in favor of partially-depleted technology, because of the difficulty in controlling the threshold voltage of fully-depleted thin-film transistors. Partially-depleted SOI (“PD-SOI”) technology has two main advantages for digital applications: the reduction of parasitic source-drain depletion capacitances and the reduction of the reverse-body effect in stack structures and pass-transistor logic.
At the device and circuit level, however, the floating body effect in PD-SOI has posed and continues to pose major challenges in the successful use of this technology. As discussed in Pong-Fei Lu et al., “Floating-body Effects in Partially Depleted SOI CMOS circuits, 32 IEEE J. Solid-State Circuits 1241 (1997), there is a parasitic bipolar effect which can result in noise failures if not correctly considered. In addition, there can be large “uncertainties” in the body potential, and consequently the threshold voltage, of devices due to unknown past switching activity. For many circuits, the design margining required to protect against this uncertainty erodes all of the potential performance advantage under nominal operation. In addition, for many circuit styles in which noise margin is strongly determined by threshold voltage (e.g. dynamic circuits), considerable overdesign for noise can also result from conservative body-voltage margining.
Several circuit design techniques, such as those described in D. H. Allen et al., “A 0.20 μm 1.8 V SOI 550 MhZ 64b Power PC Microprocessor with Cu Interconnects,” Digest Tech. Papers, ISSCC, pp. 438–39 (1999), and C. T. Chuang et al., “SOI Digital CMOS VLSI—A Design Perspective,” 36th ACM/IEEE Design Automation Concerence, pp. 709–714 (1999), attempt to contain the noise impact of the parasitic bipolar current and the delay and noise-margin variation due to the floating body. Some of these design techniques, such as predischarging internal nodes of the nFET pulldown stack in domino logic to avoid parasitic bipolar currents, are quite counter to design practice in bulk.
In addition, previous circuit-level modeling work on PD-SOI has focused either on device issues, or on delay and noise effects due to the floating-body effect evident for particular circuits under periodic stimulus, such as pulse stretching, frequency-dependent delay time. See, for example, J. Gautier et al, “On The Transient Operation of Partially Depleted SOI NMOSFET;s,” 16 IEE Electron Device Letters 498 (1995), and R. Puri et al, “Hysteresis Effect in Pass-Transistor-Based Partially-Depleted SOI CMOS Cirsuits,” Proc. Int'l SOI Conf. 1998. However, neither such modeling work nor the circuit design techniques discussed above are able to accurately estimate the upper and lower bounds of the body voltage of PD-SOI circuits in order to characterize the important electrical characteristics of the circuit. Accordingly, there exists a need in the field to accurately estimate the upper and lower bounds of the body voltage of PD-SOI circuits, taking into account the past history of the circuit, so that certain important electrical characteristics, such as delay and noise margins, of the circuit can be properly considered without requiring excessively long simulatrons.